The design process

Every schematic I release goes through the same twelve steps before anyone calls it done. Each one ties back to a line in the compliance matrix, so when verification closes out the right side of the V, there’s a concrete requirement to close against.

1. Start from a schematic that is known to work, and change it deliberately
2. Define differential pairs
3. Assign net groups and net classes
4. Set constraints at the schematic level: current, spacing, impedance
5. Simulate as much of the design as possible
6. Run failure analysis wherever it can be simulated: worst case and FMEA
7. Review the design for electrical issues
8. Run signal-integrity analysis where edge rates matter
9. Update the design requirements, and carry forward lessons from earlier parts
10. Update the parts library
11. Generate the bill of materials
12. Netlist the schematic for layout

Steps 5 and 6 are where most of this page lives. The rest of these notes walk through what that analysis looks like on a supply that has to live on a commercial vehicle.

The operating envelope

A supply on a vehicle never just sees its nominal battery voltage. It has to keep working through cold cranks, survive a double-battery jump start, ride out a load dump, and tolerate ground offsets and a reversed battery. I start every power design by drawing that envelope, because it sets the voltage rating of every part downstream.

Matching each threat to a protection

Worst-case circuit analysis

Worst-case analysis asks a simple question: if every part lands at the bad end of its tolerance, at the worst temperature, at the worst supply voltage, does the circuit still meet its requirement? I build these in MathCAD with a common set of assumptions at the top, so every subcircuit in a design is held to the same corners.

Tolerance stack

The worst-case value of a part is its initial tolerance plus its drift over the largest temperature swing from room, plus aging over life.

R_worst = R_nom × (1 ± [tol + TC × ΔT_max + aging])

Worked example: a smart high-side switch

Say a requirement calls for each output channel to carry 0.5 A with no more than 3.0 Ω of on-resistance at the hot corner. The switch I’m evaluating has a worst-case on-resistance of 0.38 Ω at 150 °C and a minimum current limit of 1.8 A. That leaves 2.62 Ω of resistance margin and 1.3 A of current-limit margin, so electrically it passes. The thermal check is where it can still fail.

P = I² × R_on,hot     T_j = T_hot + P_total × R_th

Input filter stability

Every switching supply needs an input filter to meet conducted emissions, and that filter can make a perfectly stable converter oscillate. The reason is that a regulated converter draws constant power: when its input voltage rises, its input current falls. Over the control bandwidth it looks like a negative resistance.

R_in = −V_in² / P_in

An LC filter has an output impedance that peaks at its resonant frequency. If that peak gets close to the magnitude of the converter’s negative input resistance, the two cancel and the system rings or oscillates. Middlebrook’s criterion keeps them apart: the filter’s output impedance should stay at least ten times below the converter’s input impedance, roughly 20 dB of margin.

Z_out,filter ≤ |Z_in| / 10,   so for |Z_in| = 20 Ω,   √(L/C) < 2 Ω

Damping the resonance

Undamped, an LC filter’s Q is set by whatever small resistance is left in the circuit, so the peak can be enormous. Adding R_d in series with a blocking capacitor C_d across the filter capacitor pulls Q down. The rules of thumb I use: C_d at least five times C, and R_d close to the filter’s characteristic impedance.

f₀ = 1 / (2π√(LC))    Z₀ = √(L/C)    Q = (1/R)√(L/C)    C_d ≥ 5C,   R_d ≈ Z₀

Real parts aren’t ideal

A capacitor’s impedance falls with frequency only until its self-resonant frequency. Above that, its series inductance takes over and it behaves like an inductor, so the impedance curve forms a V. That’s why I parallel a bulk capacitor with smaller ceramics in small packages: each covers a different part of the spectrum. The same thinking applies to inductors, whose winding capacitance eventually makes them look like capacitors. For mains-connected supplies, a common-mode choke with line-to-line X capacitors and line-to-chassis Y capacitors handles the two noise modes separately.

Where the noise comes from

Switching noise leaves a supply in two modes. Differential-mode noise is the pulsed input current itself, flowing out on one supply line and back on the other. Common-mode noise is sneakier: every fast voltage edge on the switch node pushes a displacement current through whatever parasitic capacitance is nearby, and that current comes home through chassis ground and the measurement network.

i = C × dv/dt     10 pF × 50 V/ns = 0.5 A

Half an amp of common-mode current from ten picofarads is why a switch tab on a grounded heatsink, or the interwinding capacitance of a transformer, can sink an otherwise good design.

Three ways to fix it, and what each costs

For radiated emissions the rules are the same whether the switch is silicon or SiC: keep the high-current switching loop physically small so it can’t act as an antenna, decouple right at the switch, and use ferrites and snubbers to damp ringing on the edges.

Measuring emissions

EMC splits into what a product puts out and what it can withstand. Both have a radiated and a conducted side, and power-quality limits sit with emissions.

Why I built a pre-compliance lab

The earlier a problem is found, the more ways there are to fix it and the less each fix costs. In simulation, a fix is a layout change. In formal compliance testing, it’s a board spin, a retest, and a schedule slip. Pre-compliance moves most of the discovery into the cheap part of that curve.

Choosing the right instrument

Conducted emissions setup

Conducted emissions put a line impedance stabilization network (LISN) between the supply and the device under test, all on a ground plane. The LISN gives the device a known, repeatable source impedance regardless of the building’s wiring, blocks noise coming in from the supply, and couples the device’s own noise out to the receiver. Note that the 50 Ω output wants a 50 Ω instrument input: on a scope, switch the channel from its 1 MΩ default.

Peak, quasi-peak, and average

Limits are written for specific detectors. Quasi-peak means “aiming toward peak but not reaching it”: it rises quickly and decays slowly, so its reading depends on how often a pulse repeats. It was designed to track how annoying impulsive interference sounds to someone listening to AM radio. Frequent pulses read close to peak; sparse pulses read much lower.

My debug process

1. Understand the device: switching frequencies, clocks, cable lengths
2. Measure it against the limit to find the failing frequencies
3. Characterize those frequencies: narrowband harmonics or broadband noise
4. Trace each one to its source with near-field probes

One trick that saves hours: park one scope channel’s near-field probe on a fixed reference point, and roam with the second. The probe that sits closest to the source shows the strongest signal, so comparing the two channels points straight at it.

Probing high-voltage switch nodes

Low-voltage rails up to about 48 V can be probed with active single-ended or differential probes. Above that, inverters, motor drives, and mid-power supplies need high-voltage differential probes with high common-mode rejection, because the switch node swings the probe’s reference along with it. Two details matter more than they look:

• Twisted leads reject interference picked up along the way but add a few picofarads of loading. Untwisted leads load the circuit less but loop interference in. I twist by default and untwist only when probe loading is the bigger problem.
• Rise-time specs are often measured with small signals. Check how a probe responds to a fast, high-voltage step, since that front edge is exactly the content you care about on a switch node.

Loop stability

A regulator’s feedback loop is what holds the output steady when the load steps, which matters most for loads that change quickly: processors, motors, display arrays. Stability is judged at the crossover frequency, where loop gain falls through 0 dB. Phase margin is how far the phase still sits above −180° at that point; I aim for 45° to 60°.

Layout and stackup

Most emissions problems are decided at layout. My default for a mixed-signal power board is a four-layer stackup with both inner layers as ground. Every signal layer then sits directly against a solid reference plane, so return currents flow right under their traces and loop areas stay small.

• Power goes on the outer layers as wide pours, so the inner ground planes stay unbroken.
• The hot loop (input capacitor, switch, and rectifier) sits on one layer with the capacitor right at the switch, keeping the loop area as small as possible.
• Stitching vias tie the two grounds together around the board edge and next to every layer change.
• Nothing gets routed across a split or gap in a reference plane.

Sources and further reading

• R. D. Middlebrook, “Input Filter Considerations in Design and Application of Switching Regulators,” IEEE Industry Applications Society Annual Meeting, 1976. The origin of the impedance criterion in section 4.
• Rohde & Schwarz application material on EMI debugging, pre-compliance measurement, SMPS common-mode noise, and high-voltage differential probing. The basis for sections 5 and 6.
• Cadence, “Physics-Based Foundations of Power Supply Design” (on-demand webinar)
• DigiKey RC and RL passive filter calculator, for quick first-order cutoff checks.
• EMC Essentials, Intensive (Wyatt Technical Services), the course behind much of how I approach EMC design.
• Standards referenced: CISPR 16-1-1, CISPR 25, ISO 7637-2, ISO 16750-2, MIL-STD-461.