Power Supply Protection and Circuit Design

Power supply design and protection

How I take a power supply from a requirement to hardware that survives the vehicle and passes EMC: the operating envelope, worst-case analysis, input-filter stability, where switching noise comes from, and how to measure it.

These are my working notes from the bench, coursework, and Allison’s pre-compliance lab. Diagrams are my own redrawings of standard concepts, and the sources I learned from are credited at the bottom. Example values are illustrative, not from any Allison product.

The design process

Every schematic I release goes through the same twelve steps before anyone calls it done. Each one ties back to a line in the compliance matrix, so when verification closes out the right side of the V, there’s a concrete requirement to close against.

  1. Start from a schematic that is known to work, and change it deliberately
  2. Define differential pairs
  3. Assign net groups and net classes
  4. Set constraints at the schematic level: current, spacing, impedance
  5. Simulate as much of the design as possible
  6. Run failure analysis wherever it can be simulated: worst case and FMEA
  7. Review the design for electrical issues
  8. Run signal-integrity analysis where edge rates matter
  9. Update the design requirements, and carry forward lessons from earlier parts
  10. Update the parts library
  11. Generate the bill of materials
  12. Netlist the schematic for layout

Steps 5 and 6 are where most of this page lives. The rest of these notes walk through what that analysis looks like on a supply that has to live on a commercial vehicle.

The operating envelope

A supply on a vehicle never just sees its nominal battery voltage. It has to keep working through cold cranks, survive a double-battery jump start, ride out a load dump, and tolerate ground offsets and a reversed battery. I start every power design by drawing that envelope, because it sets the voltage rating of every part downstream.

Supply voltage envelope for a 12/24 V commercial-vehicle module: full function 7 to 32 V, cold-crank dip to 5.5 V, jump start to 36 V, clamped load dump to 60 V, ground offset of minus 1 V, and reverse battery Full function Cold-crank dip Double-battery jump start Load dump (clamped) Ground offset Reverse battery must regulate may reset, must recover survive for minutes ms-scale pulse logic thresholds shift no damage −24 V 0 7 32 36 60 V
An example envelope for a module that has to work on both 12 V and 24 V vehicles. Amber is where the supply must regulate; outlined bars are survive-and-recover; red bars are faults the hardware has to ride out without damage. ISO 16750-2 and ISO 7637-2 define the test pulses behind these numbers.

Matching each threat to a protection

ConditionWhat it does to the circuitHow I protect against it
Reverse batteryForward-biases body diodes and reverse-biases electrolytic capacitorsSeries diode on low-current rails, or an ideal-diode MOSFET controller where the voltage drop matters
Load dumpA high-energy overvoltage pulse when the alternator loses its loadTVS sized for the pulse energy, not just its voltage, with every downstream part rated above the clamp voltage
Jump startSustained overvoltage for minutes, not millisecondsContinuous ratings, not transient ratings, on regulators and capacitors
Short to ground or overloadOutput switch heats until it failsSmart high-side switch with current limit and thermal shutdown, checked with the worst-case analysis below
Ground offsetInput thresholds move relative to the module’s own groundThresholds and hysteresis verified at the offset, not just at 0 V
Cold-crank dipBrownout resets and undefined outputsUndervoltage lockout with hysteresis and enough hold-up capacitance to finish a safe shutdown

Worst-case circuit analysis

Worst-case analysis asks a simple question: if every part lands at the bad end of its tolerance, at the worst temperature, at the worst supply voltage, does the circuit still meet its requirement? I build these in MathCAD with a common set of assumptions at the top, so every subcircuit in a design is held to the same corners.

AssumptionValue I start from
Temperature corners−40 °C cold, 25 °C room, 125 to 150 °C hot depending on mounting location
Resistor initial tolerance1%, 5%, or 10% as specified
Resistor temperature coefficient100 ppm/°C for 1% parts, 200 ppm/°C for 5% parts
Capacitor tolerance10% initial, plus 15% over temperature for X7R-class ceramics
Supply cornersThe envelope above, including the ground offset

Tolerance stack

The worst-case value of a part is its initial tolerance plus its drift over the largest temperature swing from room, plus aging over life.

Rworst = Rnom × (1 ± [tol + TC × ΔTmax + aging])

Tolerance stack calculator

Total worst-case deviation
±2.75%
Minimum value
9,725 Ω
Maximum value
10,275 Ω

A “1%” resistor is closer to 3% once a hot under-hood corner is included. That gap is why divider-based thresholds get checked at the corners, not at nominal.

Worked example: a smart high-side switch

Say a requirement calls for each output channel to carry 0.5 A with no more than 3.0 Ω of on-resistance at the hot corner. The switch I’m evaluating has a worst-case on-resistance of 0.38 Ω at 150 °C and a minimum current limit of 1.8 A. That leaves 2.62 Ω of resistance margin and 1.3 A of current-limit margin, so electrically it passes. The thermal check is where it can still fail.

P = I² × Ron,hot     Tj = Thot + Ptotal × Rth

Junction temperature check

Loss per channel
0.095 W
Package loss
0.76 W
Junction temperature
153.8 °C
Thermal margin
16.2 °C

Passes: the junction stays 16.2 °C below its limit at the hot corner.

Input filter stability

Every switching supply needs an input filter to meet conducted emissions, and that filter can make a perfectly stable converter oscillate. The reason is that a regulated converter draws constant power: when its input voltage rises, its input current falls. Over the control bandwidth it looks like a negative resistance.

Rin = −Vin² / Pin

An LC filter has an output impedance that peaks at its resonant frequency. If that peak gets close to the magnitude of the converter’s negative input resistance, the two cancel and the system rings or oscillates. Middlebrook’s criterion keeps them apart: the filter’s output impedance should stay at least ten times below the converter’s input impedance, roughly 20 dB of margin.

Zout,filter ≤ |Zin| / 10,   so for |Zin| = 20 Ω,   √(L/C) < 2 Ω

LC input filter with an Rd and Cd damping leg in parallel with the filter capacitor, feeding a switching converter that presents a negative input resistance Switching converterDraws constant powerRin= −V² / P LCCdRdBattery Z out of filterZ in of converter
The damping leg (Rd in series with Cd) flattens the resonant peak without burning power at DC, because Cd blocks the steady current.

Damping the resonance

Undamped, an LC filter’s Q is set by whatever small resistance is left in the circuit, so the peak can be enormous. Adding Rd in series with a blocking capacitor Cd across the filter capacitor pulls Q down. The rules of thumb I use: Cd at least five times C, and Rd close to the filter’s characteristic impedance.

f0 = 1 / (2π√(LC))    Z0 = √(L/C)    Q = (1/R)√(L/C)    Cd ≥ 5C,   Rd ≈ Z0

Filter response: flat to the resonant frequency, then falling at 40 dB per decade for an LC filter versus 20 dB per decade for a single pole; the undamped curve shows a sharp peak at resonance, the damped curve only a small hump 0 dBf₀log frequency Undamped peakDamped−20 dB/decade, one pole−40 dB/decade, LC
A second-order LC filter buys twice the roll-off of a single pole, which is why it’s worth the stability work. The damped curve gives up a little attenuation near f0 and nothing at the switching frequency.

LC input filter and Middlebrook check

Resonant frequency f₀
23.2 kHz
Characteristic Z₀
0.69 Ω
Converter |Rin|
19.2 Ω
Z₀ must stay below
1.92 Ω
Suggested Rd
0.69 Ω
Suggested Cd
≥ 50 µF
Attenuation at fsw
49.5 dB

Passes Middlebrook: Z₀ is 2.8× below the limit. Add the damping leg and check the peak in simulation.

Use the minimum input voltage and maximum power, since that is where |Rin| is smallest and the margin is tightest. Attenuation is the ideal −40 dB/decade estimate; real capacitors and inductors fall short of it at high frequency.

Real parts aren’t ideal

A capacitor’s impedance falls with frequency only until its self-resonant frequency. Above that, its series inductance takes over and it behaves like an inductor, so the impedance curve forms a V. That’s why I parallel a bulk capacitor with smaller ceramics in small packages: each covers a different part of the spectrum. The same thinking applies to inductors, whose winding capacitance eventually makes them look like capacitors. For mains-connected supplies, a common-mode choke with line-to-line X capacitors and line-to-chassis Y capacitors handles the two noise modes separately.

Where the noise comes from

Switching noise leaves a supply in two modes. Differential-mode noise is the pulsed input current itself, flowing out on one supply line and back on the other. Common-mode noise is sneakier: every fast voltage edge on the switch node pushes a displacement current through whatever parasitic capacitance is nearby, and that current comes home through chassis ground and the measurement network.

i = C × dv/dt     10 pF × 50 V/ns = 0.5 A

Half an amp of common-mode current from ten picofarads is why a switch tab on a grounded heatsink, or the interwinding capacitance of a transformer, can sink an otherwise good design.

Common-mode current path: displacement current from the switch node couples through parasitic capacitance into the heatsink, flows through chassis ground, and returns through the LISN and the supply lines Chassis and ground plane LISN defined 50 Ω Switching stage Switch node, fast dv/dt C parasitic Heatsink Common-mode return through chassis
The LISN is part of the loop, which is exactly why it measures this current. Shrink the parasitic capacitance or give the current a short local return, and it never reaches the LISN.

Three ways to fix it, and what each costs

ApproachHowTrade-off
Slow the edgesRaise gate resistance to lower dv/dtSimple, but adds switching loss and gives up the main advantage of SiC and GaN
Filter harderBigger common-mode choke, more Y capacitanceWorks, but adds cost, volume, and weight, and Y capacitance is capped by leakage-current limits
Fix it at the rootReduce the coupling capacitance, or return the displacement current locally, for example a capacitor from the heatsink back to the DC bus so it never reaches chassisTakes layout and mechanical work early, but costs the least in the finished product

For radiated emissions the rules are the same whether the switch is silicon or SiC: keep the high-current switching loop physically small so it can’t act as an antenna, decouple right at the switch, and use ferrites and snubbers to damp ringing on the edges.

Measuring emissions

EMC splits into what a product puts out and what it can withstand. Both have a radiated and a conducted side, and power-quality limits sit with emissions.

EMC divides into emissions (radiated near field and far field, conducted, and power quality and harmonics) and immunity (radiated and conducted susceptibility) EMC Emissions (EMI)what the product puts out Immunity (EMS)what it withstands Radiatednear and far fieldConductedPower qualityharmonicsRadiatedsusceptibilityConductedsusceptibility

Why I built a pre-compliance lab

The earlier a problem is found, the more ways there are to fix it and the less each fix costs. In simulation, a fix is a layout change. In formal compliance testing, it’s a board spin, a retest, and a schedule slip. Pre-compliance moves most of the discovery into the cheap part of that curve.

Across design phases from simulation through compliance, the number of affordable fixes falls while the cost of each fix rises sharply Fixes available and affordable Cost of each fix SimulationPre-compliance and debugPre-productionCompliance
Pre-compliance sits where fixes are still plentiful and cheap. At Allison, testing design iterations in-house avoids roughly $20,000 to $40,000 of outside-lab cost each time.

Choosing the right instrument

LevelQuestion it answersTypical tool
DiagnosticWhere is the noise coming from, and did my change help?Oscilloscope with FFT, low-cost spectrum analyzer, near-field probes
Pre-complianceHow close am I to the limit line?Spectrum analyzer or EMI receiver with CISPR 16-1-1 detectors and bandwidths, LISN, limit lines
Full complianceDoes it pass, formally?Fully compliant EMI receiver in an accredited chamber

Conducted emissions setup

Conducted emissions put a line impedance stabilization network (LISN) between the supply and the device under test, all on a ground plane. The LISN gives the device a known, repeatable source impedance regardless of the building’s wiring, blocks noise coming in from the supply, and couples the device’s own noise out to the receiver. Note that the 50 Ω output wants a 50 Ω instrument input: on a scope, switch the channel from its 1 MΩ default.

Peak, quasi-peak, and average

Limits are written for specific detectors. Quasi-peak means “aiming toward peak but not reaching it”: it rises quickly and decays slowly, so its reading depends on how often a pulse repeats. It was designed to track how annoying impulsive interference sounds to someone listening to AM radio. Frequent pulses read close to peak; sparse pulses read much lower.

For frequent pulses the quasi-peak reading sits close to peak; for sparse pulses it falls toward the average PeakQuasi-peakAverageFrequent pulsesSparse pulsesQuasi-peak
A practical consequence: scan quickly with the peak detector, then re-measure only the frequencies near the limit with quasi-peak and average. Peak is always the highest reading, so anything that passes on peak passes on all three.

My debug process

  1. Understand the device: switching frequencies, clocks, cable lengths
  2. Measure it against the limit to find the failing frequencies
  3. Characterize those frequencies: narrowband harmonics or broadband noise
  4. Trace each one to its source with near-field probes

One trick that saves hours: park one scope channel’s near-field probe on a fixed reference point, and roam with the second. The probe that sits closest to the source shows the strongest signal, so comparing the two channels points straight at it.

Probing high-voltage switch nodes

Low-voltage rails up to about 48 V can be probed with active single-ended or differential probes. Above that, inverters, motor drives, and mid-power supplies need high-voltage differential probes with high common-mode rejection, because the switch node swings the probe’s reference along with it. Two details matter more than they look:

  • Twisted leads reject interference picked up along the way but add a few picofarads of loading. Untwisted leads load the circuit less but loop interference in. I twist by default and untwist only when probe loading is the bigger problem.
  • Rise-time specs are often measured with small signals. Check how a probe responds to a fast, high-voltage step, since that front edge is exactly the content you care about on a switch node.

Loop stability

A regulator’s feedback loop is what holds the output steady when the load steps, which matters most for loads that change quickly: processors, motors, display arrays. Stability is judged at the crossover frequency, where loop gain falls through 0 dB. Phase margin is how far the phase still sits above −180° at that point; I aim for 45° to 60°.

Loop gain falls through 0 dB at the crossover frequency; phase margin is the distance between the phase curve and minus 180 degrees at that frequency. Higher input voltage raises the gain curve and moves the crossover to a higher frequency 0 dB−180°GainPhaseCrossoverPhase marginHigher Vin: crossover moves right
Gain changes with input voltage while phase barely moves, so the crossover slides along the phase curve. I check phase margin at both input-voltage corners, not just nominal.

Layout and stackup

Most emissions problems are decided at layout. My default for a mixed-signal power board is a four-layer stackup with both inner layers as ground. Every signal layer then sits directly against a solid reference plane, so return currents flow right under their traces and loop areas stay small.

Four-layer stackup: signal and power on top, ground, ground, signal and power on the bottom 1. Signal and power2. Ground planecore3. Ground plane4. Signal and power Thin prepreg between each outer layer and its ground keeps the return path tight.
  • Power goes on the outer layers as wide pours, so the inner ground planes stay unbroken.
  • The hot loop (input capacitor, switch, and rectifier) sits on one layer with the capacitor right at the switch, keeping the loop area as small as possible.
  • Stitching vias tie the two grounds together around the board edge and next to every layer change.
  • Nothing gets routed across a split or gap in a reference plane.

Sources and further reading

  • R. D. Middlebrook, “Input Filter Considerations in Design and Application of Switching Regulators,” IEEE Industry Applications Society Annual Meeting, 1976. The origin of the impedance criterion in section 4.
  • Rohde & Schwarz application material on EMI debugging, pre-compliance measurement, SMPS common-mode noise, and high-voltage differential probing. The basis for sections 5 and 6.
  • Cadence, “Physics-Based Foundations of Power Supply Design” (on-demand webinar)
  • DigiKey RC and RL passive filter calculator, for quick first-order cutoff checks.
  • EMC Essentials, Intensive (Wyatt Technical Services), the course behind much of how I approach EMC design.
  • Standards referenced: CISPR 16-1-1, CISPR 25, ISO 7637-2, ISO 16750-2, MIL-STD-461.